STM32F103C8T6 PCB Design Guide: Footprint, Pinout, and Alternatives
72 MHz Cortex-M3 MCU with 64 KB flash; the Blue Pill board chip.
The STM32F103C8T6 is the chip on the Blue Pill — the two-dollar dev board that pulled a generation of Arduino users onto 32-bit ARM. It pairs a 72 MHz Cortex-M3 with 64 KB of flash and 20 KB of SRAM in a hand-solderable LQFP48, with USB full-speed device, CAN, three USARTs, two SPI, two I2C, and two 12-bit ADCs. The part decodes from its own ordering code: C = 48 pins, 8 = 64 KB flash, T = LQFP, 6 = −40 to +85 °C.
Its popularity created a counterfeit problem unlike almost any other MCU. A large share of the F103 boards sold on marketplaces carry clone or remarked dies rather than genuine ST silicon. The clones mostly work — until a peripheral timing detail, an errata difference, or a debugger ID check bites. If your design needs the datasheet to be true, buy from authorized distribution.
Beyond provenance, F103 designs fail for a handful of repeatable hardware reasons: a missing or wrong USB pull-up resistor, loads hung on the weak PC13–PC15 pins, 5 V logic on non-tolerant pins, and a floating BOOT0. Each is covered below.
What breaks boards
Counterfeits and clones are endemic — verify your supply chain
Cheap boards frequently carry CS32F103 clones or remarked CKS/GD dies instead of genuine ST parts. Symptoms range from ST-Link reporting an unexpected IDCODE, to flash tools refusing to connect, to subtle peripheral and timing differences that only appear under load. The clones are real Cortex-M3 chips, but they are not the part this datasheet describes. For anything beyond a hobby board, buy from ST-authorized distributors and add a device-ID check to your production programming.
USB D+ needs an external 1.5 kΩ pull-up — the classic Blue Pill ships it wrong
Unlike the F4 series, the F1 has no internal USB pull-up, so your board must pull D+ (PA12) to 3.3 V through 1.5 kΩ for the host to detect a full-speed device. The original Blue Pill famously populated R10 as 10 kΩ (sometimes 4.7 kΩ), which is out of spec and breaks enumeration on some hosts. If USB is intermittent, check that resistor first. For soft connect/disconnect, switch the pull-up from a GPIO through a transistor.
PC13–PC15 are weak RTC-domain pins — LED only, not real loads
The datasheet (Table 5 note 5) states PC13–PC15 are supplied through the backup-domain power switch, which can sink only 3 mA; output use is limited to 2 MHz with a 30 pF load, and the pins must not be used as a current source, e.g. to drive an LED from the pin high. Section 5.3.13 puts their drive at ±3 mA versus ±8 mA for normal GPIOs. The onboard LED on PC13 works because it sinks a few milliamps to ground — do not copy that pattern for relays, buzzers, or anything heavier.
Only FT-marked pins are 5 V tolerant
The F103 runs from 2.0–3.6 V, and only pins marked FT in the datasheet pin table tolerate 5 V inputs — 21 of them on the LQFP48 (PA8–PA15, PB2–PB4, and PB6–PB15 except PB5). Everything else, including all the analog-capable pins on ports A0–A7 and B0/B1, is limited to VDD + 0.3 V. Check the pin table before wiring 5 V sensors or logic, and remember FT tolerance applies to digital input only, not to analog mode.
BOOT0 needs a defined level, and the hidden 128 KB is not a spec
BOOT0 selects the boot source at reset: tie it to ground through a 10 kΩ pull-down to boot from flash, and bring it high (with BOOT1/PB2 low) to enter the built-in UART bootloader for recovery. A floating BOOT0 gives intermittent startup failures. Separately, many C8 (64 KB) parts physically contain the 128 KB die and often accept code past 64 KB — useful for experiments, but it is unverified area and not guaranteed; ship only within the rated 64 KB.
Key specifications
| Parameter | Value | Source |
|---|---|---|
| Core/clock | Arm Cortex-M3, 72 MHz max | DS5319 Rev 20, cover features + Table 2 |
| Flash | 64 KB | DS5319 Rev 20, Table 2 + Section 7 ordering scheme ('8 = 64 Kbytes') |
| SRAM | 20 KB | DS5319 Rev 20, Table 2 |
| VDD range | 2.0–3.6 V | DS5319 Rev 20, Table 2 (operating voltage) + cover features |
| 5 V-tolerant pin count | 21 FT pins on LQFP48 (PA8–PA15, PB2–PB4, PB6–PB15 except PB5) | DS5319 Rev 20, Table 5 pin definitions (note 2: FT = 5 V tolerant) |
| ADC channels/resolution | 2× 12-bit ADC, 10 external channels on 48-pin package | DS5319 Rev 20, Table 2 (STM32F103Cx column) |
| Package | LQFP48, 7 × 7 mm | DS5319 Rev 20, cover + Table 2 packages row |
Verified against the manufacturer datasheet on 2026-07-09. Confirm the current revision before production use.
Alternatives
- STM32F401CCU6 — the Black Pill upgrade: Cortex-M4F with FPU and more SRAM, but a different pinout and board layout — not a drop-in for existing F103 designs.
- GD32F103C8T6 — GigaDevice's faster clone (108 MHz capable) that is pin-compatible and mostly register-compatible, with known peripheral timing quirks — validate USB and flash wait states.
- CH32V203C8T6 — WCH's cheap pin-compatible RISC-V take on the footprint; needs a different toolchain and its peripherals are similar but not identical.
Common questions
- How do I tell a fake STM32F103C8T6 from a real one?
- Connect a debugger and check the device ID: clones such as the CS32 report a different IDCODE than genuine ST silicon, and programming tools may warn or refuse. Marking quality and lot codes help but are easy to fake. The only reliable prevention is buying from ST-authorized distribution.
- Why won't my Blue Pill enumerate over USB?
- Most often the D+ pull-up: the F103 has no internal USB pull-up, and the classic Blue Pill shipped R10 as 10 kΩ instead of the required 1.5 kΩ to 3.3 V. Replace it with 1.5 kΩ and most hosts will detect the board reliably.
- How should BOOT0 be wired on an STM32F103 board?
- Pull BOOT0 to ground through roughly 10 kΩ so the chip boots from main flash. To use the factory UART bootloader for recovery or first programming, drive BOOT0 high at reset with BOOT1 (PB2) low. Never leave BOOT0 floating.
- Which STM32F103C8T6 pins are 5 V tolerant?
- Only the pins marked FT in the datasheet pin table — 21 of the LQFP48's I/Os: PA8–PA15, PB2–PB4, and PB6–PB15 except PB5. All other pins, including every ADC-capable pin, are limited to VDD + 0.3 V, so 5 V signals there need level shifting.